1. Field of the Invention
The present invention relates to a signal processing circuit such as a neural network etc for implementing a parallel pulse signal process involving a local synchronous behavior.
2. Related Background Art
Image and voice recognition implementation systems have hitherto been roughly classified into such a type that a recognition processing algorithm specialized for a specified recognition object is sequentially operated and executed as computer software, and a type in which the same algorithm is executed by a dedicated parallel image processor (such as an SIMD (Single Instruction Multiple Data) processor, an MIMD (Multiple Instruction stream/Multiple Data stream) processor and so on).
Typical examples are given below as exemplifying the image recognition algorithm. At first, the following is methods involving calculating a feature amount relative to a similarity to a recognition object model. One method is a method for representing recognition object model data as a template model, calculating a similarity by template matching etc with an input image (or a feature vector thereof) and calculating a high-order correlation coefficient. Another method is a method (Sirovich, et al., 1987, Low-dimensional procedure for the characterization of human faces, J. Opt. Soc. Am. (A), vol. 3, pp. 519–524) for mapping an input pattern to an intrinsic image function space obtained by analyzing primary components of an object model image, and calculating an intra-feature-space distance from the model. A further method is a method (Lades et al., 1993, Distortion Invariant Object Recognition in the Dynamic Link Architecture, IEE Trans. on Computers, vol. 42, pp. 300–311) for representing a plurality of feature extraction results (feature vectors) and a spatial arrangement relationship as graphs, and calculating a similarity based on elastic graph matching. A still further method is a method (Seibert, et al., 1992, Learning and recognizing 3D objects from multiple views in a neural system, in Neural Networks for Perception, vol. 1 Human and Machine Perception (H. Wechsler Ed.) Academic Press, pp. 427–444) for obtaining position-, rotation- and scale-invariable representations by executing predetermined conversions with respect to input images and thereafter collating with a model.
The following is exemplifications of a pattern recognition method based on a neural network model of which a hint is acquired from a biological information processing system. One exemplification is a method (Japanese Patent Post-Exam. No. 60-712, Fukushima & Miyake, 1982, Neocognitron: A new algorithm for pattern recognition tolerant of deformation and shifts in position, Pattern Recognition, vol. 15, pp-455–469) for implementing hierarchical template matching. Another exemplification is a method (Anderson, et al., 1995, Routing Networks in Visual Cortex, in Handbook of Brain Theory and Neural Networks (M. Arbib, Ed.), MIT Press, pp. 823–826) for obtaining object-based scale- and position-invariable representations by dynamic routing neural networks. Other exemplifications are methods using multi-layer perceptrons, a radial basis function network and so on.
On the other hand, what is proposed as a scheme for taking an information processing system based on biological neural networks with a higher fidelity, is a neural network model circuit (Murray et al., 1991, Pulse-Stream VLSI Neural Networks Mixing analog and digital Techniques, IEEE Trans. on Neural Networks, vol. 1.2, pp. 193–204,; Japanese Patent Application Laid-Open Nos. 7-262157, 7-334478 and 8-153148, and Japanese Patent Publication No. 2,879,670) for transmitting and representing information through on a pulse train corresponding to an action potential.
Methods for recognizing and detecting a specified object by a neural network constructed of pulse train generation neurons, are systems (U.S. Pat. No. 5,664,065, and Broussard, et al., 1999, Physiologically Motivated Image Fusion for Object Detection using a Pulse Coupled Neural Network, IEEE Trans. on Neural Networks, vol. 10, pp. 554–563, and so forth) using a pulse coupled neural network (which will hereinafter be abbreviated to PCNN), to be specific, a high-order (second-order or higher) model by Echhorn (Eckhorn, et al., 1990, Feature linking via synchronization among distributed assembles: simulation of results from cat cortex, Neural Computation, vol. 2, pp. 293–307) which is based on the premise of linking inputs and feeding inputs.
Further, a method for relieving a wiring problem in the neural network is an event-driven oriented method (Address Event Representation: this will hereinafter be abbreviated to AER) (Lazzaro, et al., 1993, silicon Auditory Processors as Computer Peripherals, In Touretzky, D (ed), Advances in Neural Information Processing Systems 5. San Mateo, Calif.: Morgan Kaufmann Publishers) for coding addresses of so-called pulse output neurons. In this case, IDs of pulse train output-sided neurons are coded as binary addresses, whereby even when output signals from the different neurons are arranged in time sequence on a common bus, the input-sided neurons are able to automatically decode the addresses of the source neurons.
On the other hand, the neural network processor related to U.S. Pat. No. 2,741,793 schemes to reduce the number of neurons and to downsize a circuit by configuring multi-layered feedforward oriented networks in a systolic array architecture.
According to the parallel processing multiprocessors system etc related to Japanese Patent Publication No. 2,500,038, an existence or non-existence of error is detected based on a decision-by-majority process of signatures generated simultaneously with a process of an instruction set in a distributed parallel type computing system.
Moreover, the operation frequency of the microprocessors have shown sharp increases over the recent years. Under this condition, there is developed an architecture (Schuster, S. et al., “Asynchronous Interlocked Pipelined CMOS Circuits operating at 3.3–4.5 GHz”, 2000, IEEE International solid-state circuits conference (ISSCC2000), WA17.3, vol. 43, pp. 292–293, 2000) in which the whole chip is not operated in synchronization with the single clock signal, and the chip is divided into a plurality of blocks and these blocks are operated asynchronously.
The prior arts described above are required to use global clock signals as control clock signals for taking synchronism of arithmetic elements, and to use local clock signals as control clock signals for forming a synchronization cluster for performing a local behavior.
This architecture brings about increases both in circuit scale and in consumption of electric power, and is difficult to actualize a synchronization circuit operating stably without any contradiction.